Regviz

Alif Semiconductor /AE512F80F5582LS_CM55_HE_View /DMA2_SEC /DMA_INT_EVENT_RIS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DMA_INT_EVENT_RIS

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Alif Semiconductor/AE512F80F5582LS_CM55_HE_View/DMA2_SEC/DMA_INT_EVENT_RIS#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMASEV_ACTIVE

Description

Event-Interrupt Raw Status Register

Fields

DMASEV_ACTIVE

This bit field returns the status of the event-interrupt resources.

  • Bit [N] = 0x0: Event N is inactive or IRQ[N] is low.
  • Bit [N] = 0x1: Event N is active or IRQ[N] is high. Note: When the DMAC executes a DMASEV N instruction to send event N, the DMA_INTEN register controls whether the DMAC:
  • Signals an interrupt using the appropriate IRQ.
  • Sends the event to all of the threads (see DMA_INTEN register). Note: The DMAC clears bit [N] when either:
  • The DMA_INTEN register is programmed to process the event and the DMAC executes a DMAWFE instruction for that event.
  • The DMA_INTEN register is programmed to signal an interrupt and the user write to the corresponding bit in the DMA_INTCLR register.

Links

()

Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data